This invention relates to an integrated circuit tester with a test head including a regulating capacitor.
An integrated circuit tester is used to predict how an integrated circuit device will behave in operation. A typical integrated circuit tester includes a test head having multiple tester modules, each of which has a signal terminal. Each tester module includes pin electronics circuitry which operates the module selectively in one of several operating modes, which typically include drive high, drive low, compare high and compare low. In the drive high mode, for example, the circuitry applies a logic high signal to the signal terminal, whereas in the compare low mode, the circuitry compares the voltage at the signal terminal with a low threshold value. In order to carry out a test, the test head is positioned with the signal terminals of the tester modules in contact with respective signal I/O pads of a load board. The load board provides a parallel electrical interface between the signal terminals of the tester modules and signal pins of the device under test (DUT).
The tester includes a device power supply (DPS) having force and return terminals connected through the load board to respective power supply pins of the DUT to supply operating current to the DUT. A test is executed in a succession of cycles, and for each cycle of the test, each tester module is placed in a selected one of its predetermined operating modes. In this manner, the DUT is exercised through a sequence of internal states, and the nature of the output of the DUT in each state is observed. In the case of a complex DUT, there may be many thousands of test cycles and therefore the testing can take a long time.
Two aspects of testing of an integrated circuit device are functional testing and quiescent current testing. The purpose of functional testing is to determine whether the DUT provides the expected output in each state. The purpose of quiescent current testing is to detect anomalies in current consumption by measuring the current drawn by the DUT in steady state, when there are no changes in state occurring. In a high speed functional test, the DPS may supply several amps of current, whereas a much smaller current is drawn during quiescent current testing.
FIG. 3 illustrates schematically a tester and a load board configured for measuring quiescent current drawn by a DUT 10. A DPS 12 for supplying operating current to the DUT includes a power supply amplifier 14 whose output is connected through a current sensing resistor 16 to the V.sub.DD terminal of the DUT. A differential amplifier 18 is connected across the sensing resistor and provides an output signal representative of the current flowing through the resistor. A bypass capacitor 20 is connected between the force and return lines of the DPS 12 to regulate the voltage applied to the power supply pins of the DUT. The tester includes multiple tester modules 22, only one of which is shown, connected to respective signal pins of the DUT.
In order to carry out a functional test, the test modules exercise the DUT through a sequence of states and acquire data indicating the behavior of the DUT in each state, as mentioned above. In order to measure quiescent current, the DUT must first be sensitized to a particular target state. In general, this is accomplished by using the tester modules to apply signals to the DUT and thereby advance the DUT through a pattern of states until the target state is reached. During sensitizing of the DUT, substantial current may be drawn as the DUT changes state. When the DUT has been sensitized to the target state, the current drawn by the DUT is measured by digitizing the output signal of the differential amplifier 18.
In order to regulate the voltage adequately during the functional test and during sensitizing of the DUT to its target state, the bypass capacitor 20 should normally have a capacitance C of from 10 to 100 .mu.F. However, a bypass capacitance of less than one percent of C will generally be sufficient to regulate the voltage during a quiescent current measurement. If the quiescent current is measured with a large bypass capacitance, the bypass capacitance will introduce substantial current noise in the current measurement circuit.
Before measuring quiescent current, it is necessary to allow the current to settle to a steady value. The settling time depends on the capacitance between the force and return lines of the DPS. Accordingly, use of a large bypass capacitance increases the time taken to carry out a quiescent current test.
FIG. 4 illustrates a tester which avoids some of the disadvantages of the tester shown in FIG. 3. In accordance with FIG. 4, a capacitor 26 of fairly small capacitance C1 (e.g. 0.1 .mu.F) is connected between the force and return lines and a circuit branch consisting of an electromechanical relay switch 28 and a capacitor 30 of substantially larger capacitance C2 (e.g. 10 to 100 .mu.F), connected in series, is connected in parallel with the capacitor 26. In order to carry out a functional test or sensitize the DUT, the electromechanical relay switch 28 is closed and accordingly the bypass capacitance is (C1+C2), whereas in order to measure the quiescent current the relay switch 28 is opened and the capacitor 30 is taken out of circuit so that the bypass capacitance is C1.
A thorough test of a complex integrated circuit device would involve quiescent current testing in thousands of states. The time for switching the relay 28 may be as long as 50 ms, depending on the size of the relay which, in turn, depends on the maximum current drawn by the DUT. The switching time is such that it is impractical to measure quiescent current at each pertinent state of the device and accordingly it has hitherto been conventional to measure quiescent current at relatively few states. There is therefore a significant danger that an anomaly in quiescent current will not be detected, and a defective device might not be discovered.
Generally, each different design of integrated circuit device to be tested requires a different load board to interface with the tester, and consequently the cost of the load board can be a significant component of the cost of testing a device. The large capacitance bypass capacitor 30 is typically a ceramic capacitor and is therefore expensive. Further, the electromechanical relay switch 28 also is expensive. Since the relay switch 28 and the capacitor 30 are mounted on the load board, the cost of the relay switch and the ceramic capacitor is a component of the cost of the load board and consequently, the cost of test of a particular device.
A VLSI tester may be able to test a device having more than one thousand pins. However, many devices have only several hundred pins, and it may be desirable to test multiple devices concurrently by designing the load board to provide connections to multiple devices.
The load board is carried by a displacement mechanism, such as a wafer prober or a device handler, which displaces the load board to and from the position in which the signal I/O pads of the load board contact the signal terminals of the tester modules. The physical structure of the displacement mechanism, and the need to avoid collision between the load board and other components of the tester as the displacement mechanism displaces the load board, imposes a limit on the size of the load board and hence on the space available on the load board to support multiple devices.
If the arrangement shown in FIG. 4 is used to test multiple devices concurrently, there must be an electromechanical switch 28 and a capacitor 30 on the load board for each DUT. The electromechanical relay switch 28 and the ceramic capacitor 30 are bulky and therefore placing them on the load board limits the space available in the load board for devices to be tested.
It is desirable that the contact pads on the load board be brought as close as possible to the test head in order to minimize the uncompensated inductance of conductors, such as pogo pins, connecting the test head to the load board. Since the capacitor 30 and the electromechanical relay switch are bulky, the presence of these components on the load board establishes a minimum spacing of the load board from the test head.
The manufacturer of the tester generally cannot control the choices made by the user of the tester in manufacture of the load board. If the user selects an unsuitable capacitance value for the capacitor 30, the validity of the test results provided by the tester may be impaired. Also, if the user makes an unsuitable choice in the location of the capacitor 30 and the electromechanical relay switch 28 on the load board, the validity of the test results may be impaired.